Design of a High PSRR Multistage LDO with On-Chip Output Capacitor

Konferenz: SMACD / PRIME 2021 - International Conference on SMACD and 16th Conference on PRIME
19.07.2021 - 22.07.2021 in online

Tagungsband: SMACD / PRIME 2021

Seiten: 4Sprache: EnglischTyp: PDF

Zoche, Jonas; Hanhart, Michael; Grobe, Jan; Weihs, Leon; Rolff, Leo; Wunderlich, Ralf; Heinen, Stefan (Chair of Integrated Analog Circuits and RF Systems, RWTH Aachen University, Aachen, Germany)

This paper proposes a high PSRR LDO design, implemented in a 0.18 µm BCD technology using, only on-chip capacitors. Multiple stages in series with PMOS pass transistors lead to high PSRR, small drop-out voltage, and low circuit complexity in comparison to designs relying on ripple feedforward. Without external capacitors, the presented auxiliary LDO does not increase the pin count while the multistage approach leads to low circuit complexity. Overall, 54 dB PSRR are achieved across corners up to 10 GHz with a quiescent current of 15:5 muA and 0.192 µm2 chip area.