Skew and Jitter Performance in CMOS Clock Phase Splitter Circuits

Konferenz: SMACD / PRIME 2021 - International Conference on SMACD and 16th Conference on PRIME
19.07.2021 - 22.07.2021 in online

Tagungsband: SMACD / PRIME 2021

Seiten: 4Sprache: EnglischTyp: PDF

Scaletti, Lorenzo; Parisi, Angelo; Bertulessi, Luca (Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Milano, Italy)

This paper compares two different clock phase splitter architectures: the first is based on the standard XOR gate splitter topology, the other exploits the concept of phase interpolation. The comparison, supported by schematic simulations, shows that the phase interpolating splitter outperforms the XOR gate based topology with no penalty in power consumption. In particular, the output jitter is reduced by 15% while the skew between the output phases is reduced by about 80%. The phase interpolating splitter, implemented in 28nm bulk CMOS, achieves jitter lower than 35fs with power consumption lower than 5mW at 1GHz input frequency in post-layout simulations. The skew between the generated output signals is always lower than 10ps.