Make Some Noise: Energy-Efficient 38 Gbit/s Wide-Range Fully-Configurable Linear Feedback Shift Register

Konferenz: SMACD / PRIME 2021 - International Conference on SMACD and 16th Conference on PRIME
19.07.2021 - 22.07.2021 in online

Tagungsband: SMACD / PRIME 2021

Seiten: 4Sprache: EnglischTyp: PDF

Wagner, Christoph W. (Technische Universität Ilmenau, Institute for Information Technology, Ilmenau, Germany)
Glaeser, Georg (IMMS Institut für Mikroelektronik- und Mechatronik-Systeme gemeinnützige GmbH (IMMS GmbH), Ilmenau, Germany)
Sasse, Thomas (Technische Universität Ilmenau, Institute for Mathematics, Ilmenau, Germany)
Kell, Gerald (Technische Hochschule Brandenburg, Fachbereich für Informatik und Medien, Brandenburg, Germany)
Del Galdo, Giovanni (Technische Universität Ilmenau, Institute for Information Technology, Ilmenau, Germany & Fraunhofer IIS, Fraunhofer Institute for Integrated Circuits IIS, Ilmenau, Germany)

Compressed Sensing (CS) and Radio Detection and Ranging (RADAR) Systems require stimulus signals with properties similar to true random signals, but deterministic and reproducible in hardware. Therefore, Pseudo-Random Noise (PRN) sequences render ideal for this purpose. Especially mm-Wave systems require very high symbol rates and hence operating frequencies. Being able to choose a PRN signal is key to achieving good system performance by means of high operating frequency and energy consumption. For operating near the extreme limits of the technology, we propose an energy-efficient fully-configurable Linear Feedback Shift Register (LFSR) architecture with synchronous reset for PRN generation based on Positive Emitter Coupled Logic (PECL). By choosing a shift-register based multi-data-rate (MDR) structure, we shift the logic paths to a low-frequency domain. Further, we construct the register from small elementary slices with two levels of Power-Shut-Off (PSO) functionality for reducing the power consumption from 12% to 69%. We prove our architecture in 130nm SiGe BiCMOS technology, using transistor-level simulations and calibrated fab models. The register of length 24 is shown to operate correctly up to f0=38:5 GHz, corresponding to approximately equal to 1/6th of the process transition frequency. Our design draws 180mW to 510mW from a 2:50V supply at a die area of 0:10mm2 (includes serializer).