Resource Efficient Sub-VT Level Shifter Circuit Design Using a Hybrid Topology in 28 nm
Konferenz: SMACD / PRIME 2021 - International Conference on SMACD and 16th Conference on PRIME
19.07.2021 - 22.07.2021 in online
Tagungsband: SMACD / PRIME 2021
Seiten: 4Sprache: EnglischTyp: PDF
Chatterjee, Saikat; Rueckert, Ulrich (Cognitronics and Sensor Systems Group, CITEC, Bielefeld University, Germany)
This paper presents a resource efficient level shifter circuit, which is capable of converting input voltages below subthreshold to above threshold voltages, making it suitable for ultra low power applications such as wireless sensor networks, biomedical implants, environmental sensors, to name a few. The proposed circuit topology has two stages. The first stage comprises of a Wilson current mirror, whereas the second stage has a cross coupled PMOS circuit. The two staged topology helps to overcome the challenges of deep nano process, when operated with ultra low input supply voltage. The circuit presented here, is implemented in 28nm FDSOI technology from ST Microelectronics. The proposed level shifter is capable of converting an input voltage as low as 150mV to 1V. The static power consumption is measured to be 100pW, when the circuit is operated with the minimum possible input supply and operational frequency of 500 kHz.