Data Prep – The Bottleneck of Future Applications?

Konferenz: EMLC 2006 - 22nd European Mask and Lithography Conference
23.01.2006 - 26.01.2006 in Dresden, Germany

Tagungsband: EMLC 2006

Seiten: 11Sprache: EnglischTyp: PDF

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Gramss, Juergen; Eichhorn, Hans; Lemke, Melchior; Jaritz, Renate; Neick, Volker; Beyer, Dirk (Leica Microsystems Lithography GmbH; Goeschwitzer Strasse 25, 07745 Jena, Germany)
Buerger, Bertram; Baetz, Ulrich; Kunze, Klaus (Fraunhofer IPMS, Maria-Reiche-Str. 2, 01109 Dresden, Germany)
Belic, Nikola (PDF Solutions GmbH, Isartorplatz 8, 80331 Munich / Germany)

There is no doubt that shaped beam systems have been well established in the mask write community since the introduction of the 130nm technology node. Moreover, they are successfully advancing to conquer also the wafer direct write market. To be able to handle today and in the near future the tremendous data volumes with their characteristic complexity as well as to make use of such indispensable methods like PEC and Fogging corrections, new, sophisticated solutions are necessary to master the challenging 45nm technology node. However, we are aware that the 45nm node presents only an intermediate step, because, according to the international roadmap, we soon will be confronted with the hardware and software requirements of the next, the 32nm technology node. In this context it becomes more and more important to consider potential showstoppers, in our case the data preparation process To investigate this complex subject a Linux cluster computer featuring 3.6GHz clock rate CPUs, and a software package supporting distributed computing with a 64Bit version and address units down to 0.1nm were used. The work was focussed on the performance of pattern samples down to the 45nm node. Both mask and wafer data as well as NIL template manufacturing were considered, data prep times and CPU loads were analysed. Furthermore, the user-friendly Leica Interface for Data Preparations (LINDA) was applied. In addition, an outlook to future hardware/software configurations for mastering the challenges of the 32nm node will be given. The results presented in this paper prove that data preparation is not the bottleneck of current and future applications.