A Defect Oriented Circuit Simulation Approach Applied to D-RAM Designs

Konferenz: Zuverlässigkeit und Entwurf - 1. GMM/GI/ITG-Fachtagung
26.03.2007 - 28.03.2007 in München, Germany

Tagungsband: Zuverlässigkeit und Entwurf

Seiten: 2Sprache: EnglischTyp: PDF

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Versen, Martin; Kneževic, Jelena; Montoya, Sergio M. (Qimonda AG, PD PT PRE O, Neubiberg, Germany)
Vermeiren, Wolfgang; Coym, Torsten; Straube, Bernd (Fraunhofer-Institut für Integrierte Schaltungen, Institutsteil Entwurfsautomatisierung, Zeunerstr. 38, 01069 Dresden, Germany)

In this work essential parts of a DRAM circuit are studied with respect to their transient behavior in the presence of defects. A certain dynamic failure mechanism resulting from timing mismatches of signals is addressed. The necessary fault lists for the analog fault simulations take the circuit’s layout geometry into consideration and are generated with the aid of parasitic element extraction tools. The establishment of a mapping between the circuit layout and the electrical network reveals new facts about the robustness of the design and the efficiency of the existing test solutions.