Towards an integrated inverter based on lateral JFET SiC
Konferenz: CIPS 2006 - 4th International Conference on Integrated Power Systems
07.06.2006 - 09.06.2006 in Naples, Italy
Tagungsband: CIPS 2006
Seiten: 6Sprache: EnglischTyp: PDFPersönliche VDE-Mitglieder erhalten auf diesen Artikel 10% Rabatt
Gié, J.; Lazar, M.; Planson, D.; Bergogne, D.; Bevilacqua, P.; Allard, B.; M'Rad, S. (ISP3D/CEGELY, CNRS UMR 5005, Bât L. de Vinci, 20Av. A. Einstein, 69621 Villeurbanne Cdx, France)
The feasibility of a hybrid inverter based on commercial silicon carbide vertical JFETs was tested. The Ron-resistance, mainly due to the vertical channel, increases with the temperature, from 1.1 Ω measured at RT to 2.98 Ω at 300deg C. These devices can drive current in both forward and reverse direction, eliminating the need for an external anti-parallel diode. A transient current-limited short circuit is observed with duration of 100 ns in turn-on. The power losses estimated involve for the hybrid inverter a working frequency up to 300 kHz. Good results obtained for hybrid inverter predict a SiC monolithic inverter realization. For this propose, SiC lateral JFETs (LJFETs) were studied and designed by finite-element method. A double RESURF structure is retained for the SiC LJFET, in order to reduce the on-resistance and to improve the blocking voltage. The obtained Ron-resistances are one order of magnitude lower than in vertical SiC JFETs. This result is obtained thanks to the high doping lateral channel and RESURF structure. Switching times of the LJFETs during turn-off and turn-on, are obtained in the 20 to 30 ns range. Eight levels of masks are designed to fabricate these devices. The masks structures were optimized in order to minimize both the Ron-resistance and the device size by utilizing inter-fingers structures.