Review of DVS techniques to reduce power consumption of digital circuits
Konferenz: CIPS 2006 - 4th International Conference on Integrated Power Systems
07.06.2006 - 09.06.2006 in Naples, Italy
Tagungsband: CIPS 2006
Seiten: 6Sprache: EnglischTyp: PDFPersönliche VDE-Mitglieder erhalten auf diesen Artikel 10% Rabatt
Huerta, S. C.; Vasic, M.; Castro, A. de; Alou, P.; Cobos, J. A. (Universidad Politécnica de Madrid (UPM), División de Ingeniería Electrónica (DIE), José Gutiérrez Abascal, 2, 28006 Madrid, SPAIN)
DVS (Dynamic Voltage Scaling) is a technique used for reducing the power consumption of microprocessors. The power consumed by these circuits has a main component (dynamic power) that is proportional to the square of the supply voltage. Additionally, for every supply voltage, there is a,maximum value of the clock frequency . The advantage of using DVS is that the supply voltage (and hence clock frequency) can be adjusted depending on the specific needs during execution. The DVS concept has been used in some commercial products like Transmeta’s Crusoe, Intel Speed Step, AMD K6, Hitachi SH4, etc. However, microprocessors are not the only possible platform for DVS. FPGAs or ASICs are also possible. An example using an ASIC is presented in "Burd, T. D.; Brodersen, R. W.; Pering A. T.; Stratakos A. J.: A Dynamic Voltage Scaled Microprocessor System" where an ARM8 was synthesized in the ASIC. In this paper, we discuss the state of the art of DVS, the advantages of using DVS and some results obtained by using DVS in some commercial products. The most important characteristics of each device that makes use of DVS are shown, as well as other important blocks that are necessary for the implementation of DVS (software, hardware, power supply and DVS scheduler).