Planarization of the Poly-Si gate for Non Volatile Memories

Konferenz: ICPT 2007 - International Conference on Planarization / CMP Technology
25.10.2007 - 27.10.2007 in Dresden, Germany

Tagungsband: ICPT 2007

Seiten: 5Sprache: EnglischTyp: PDF

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Baud, L. (CEA-LETI Minatec, 17 rue des Martyrs, 38054 Grenoble, France)
Canevari, L.; Romanelli, C.; Spinolo, G. (ST Microelectronics,Via C. Olivetti 2, 20041 Agrate Brianza, Italy)
Rivoire, M. (ST Microelectronics, 850 rue Jean Monnet, BP 16, 38921 Crolles, France)

In order to achieve flat topography on Poly-Si films, effects of the slurry components and process parameters were studied using different ceria particles and additives. Abrasive particles size has a major effect on planarization efficiency. Also additives types and ratio are the key to achieve high selectivity to topography and self-stopping effect. However polishing pressure does not help to reduce wafer topography on Poly-Si films. A self-stopping Poly-Si CMP process is still required to achieve complete flatness without any poly consumption on bottom areas.