Influence of STI Trench Fill and Dummy Design on CMP Behavior
Konferenz: ICPT 2007 - International Conference on Planarization / CMP Technology
25.10.2007 - 27.10.2007 in Dresden, Germany
Tagungsband: ICPT 2007
Seiten: 6Sprache: EnglischTyp: PDFPersönliche VDE-Mitglieder erhalten auf diesen Artikel 10% Rabatt
Ong, P.; Devriendt, K.; Redolfi, A.; Hernandez, J. L. (IMEC vzw, Kapeldreef 75, B-3001 Leuven, Belgium)
Okuno, Y. (Matsushita assignee to IMEC)
Shallow Trench Isolation (STI) is the process of choice for the isolation of the transistors of Complimentary Metal Oxide Semiconductor (CMOS) devices for technology nodes smaller than 0.25 µm. Chemical Mechanical Polishing (CMP) process is an essential part of the STI module. Since the 0.13 µm technology node the industry standard is a direct STI CMP approach, where the oxide used to fill the trenches is polished directly without any combined dry etchback process. The most common trench fill process is High Density Plasma Chemical Vapor Deposition (HDP CVD). However, for the more challenging fill requirements of the 45 nm technology node and beyond, Sub-Atmospheric Chemical Vapor Deposition (SACVD) processes are evaluated. The resulting SACVD oxide film has a very different filling behavior than HDP oxide films, which also results in a different polishing behavior. Based on this different fill behavior the authors propose an effective area ratio (EAR) model, which is used to determine a dummy fill optimized specifically for SACVD films. First results of wafers with this new dummy design demonstrate a reduction in polishing time enabling higher throughput and reducing process costs.