Speeding Things Up: Reducing the Processing Overhead in Real Time Ethernet Communications using FPGA's

Konferenz: SPS/IPC/DRIVES 2007 - SPS/IPC/DRIVES/Elektrische Automatisierung - Systeme und Komponenten - Fachmesse & Kongress
27.11.2007 - 29.11.2007 in Nürnberg, Germany

Tagungsband: SPS/IPC/DRIVES 2007

Seiten: 5Sprache: EnglischTyp: PDF

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Doran, Hans Dermot (Zürich University of Applied Sciences, Institute of Embedded Systems, Winterthur, Switzerland)

Real Time Ethernet (RTE) is fast, dependable, and consumes processing power like no other field-bus before it. This simple fact has radically changed the face of hardware architectures for field-bus systems yet arguably slowed the adoption of such technology. One of the main arguments for the use of such technology is the cost advantage of high speed communication coupled with low-cost standard Ethernet components. An intuitive argument until one looks at the footprint of these components as well as the fact that the main Ethernet component, the MAC, is hardly available without a PCI interface. This reduces possible design-in scenarios to precisely three; Use of a microcontroller with an integrated Ethernet MAC; Use of an FPGA; Use of an ASIC.