Controlling Linewidth Roughness in Step and Flash Imprint Lithography

Konferenz: EMLC 2008 - 24th European Mask and Lithography Conference
21.01.2008 - 24.01.2008 in Dresden, Germany

Tagungsband: EMLC 2008

Seiten: 10Sprache: EnglischTyp: PDF

Persönliche VDE-Mitglieder erhalten auf diesen Artikel 10% Rabatt

Schmid, Gerard M.; Khusnatdinov, Niyaz; Brooks, Cynthia B.; LaBrake, Dwayne; Thompson, Ecron; Resnick, Douglas J. (Molecular Imprints, Inc., 1807C West Braker Lane, Austin TX 78758, USA)
Owens, Jordan; Ford, Arnie (Sematech ATDF, 2706 Montopolis Drive, Austin, Texas 78741-6499, USA)
Sasaki, Shiho; Toyama, Nobuhito; Kurihara, Masaaki; Hayashi, Naoya (Electronic Device Laboratory, Dai Nippon Printing Co., Ltd., 2-2-1, Fukuoka, Fujimino-shi, Saitama 356-8507, Japan)
Kobayashi, Hideo; Sato, Takashi; Nagarekawa, Osamu (HOYA Corporation R&D Center 3-3-1 Musashino,Akishima-shi,Tokyo 196-8510 Japan)
Hart, Mark W.; Gopalakrishnan, Kailash; Shenoy, Rohit; Jih, Ron (IBM Almaden Research Center, 650 Harry Road San Jose, CA 95120-6099, USA)
Zhang, Ying; Sikorski, Edmund; Rothwell, Mary Beth (IBM Thomas J. Watson Research Center, 1101 Kitchawan Road, Route 134Yorktown Heights, NY, 10598-0218, USA)
Yoshitake, Shusuke; Sunaoshi, Hitoshi; Yasui, Kenichi (NuFlare Technology, Inc., 8, Shinsugita-cho, Isogo-ku, Yokohama 235-0032, Japan)

Despite the remarkable progress made in extending optical lithography to deep sub-wavelength imaging, the limit for the technology seems imminent. At 22nm half pitch design rules, neither very high NA tools (NA 1.6), nor techniques such as double patterning are likely to be sufficient. One of the key challenges in patterning features with these dimensions is the ability to minimize feature roughness while maintaining reasonable process throughput. This limitation is particularly challenging for electron and photon based NGL technologies, where fast chemically amplified resists are used to define the patterned images. Control of linewidth roughness (LWR) is critical, since it adversely affects device speed and timing in CMOS circuits. Imprint lithography has been included on the ITRS Lithography Roadmap at the 32 and 22 nm nodes. This technology has been shown to be an effective method for replication of nanometer-scale structures from a template (imprint mask). As a high fidelity replication process, the resolution of imprint lithography is determined by the ability to create a master template having the required dimensions. Although the imprint process itself adds no additional linewidth roughness to the patterning process, the burden of minimizing LWR falls to the template fabrication process. Non chemically amplified resists, such as ZEP520A, are not nearly as sensitive but have excellent resolution and can produce features with very low LWR. The purpose of this paper is to characterize LWR for the entire imprint lithography process, from template fabrication to the final patterned substrate. Three experiments were performed documenting LWR in the template, imprint, and after pattern transfer. On average, LWR was extremely low (less than 3nm, 3sigma), and independent of the processing step and feature size.