An Automated Flow for 3D Chip Stack Estimation

Konferenz: edaWorkshop 10 - Workshop 2010 - Electronic Design Automation (EDA)
04.05.2010 - 05.05.2010 in Hannover, Germany

Tagungsband: edaWorkshop 10

Seiten: 5Sprache: EnglischTyp: PDF

Persönliche VDE-Mitglieder erhalten auf diesen Artikel 10% Rabatt

Schuster, Thomas; Kranich, Tim; Hanke, Matthias; Berekovic, Mladen (Institute of Computer and Network Engineering, TU Braunschweig, Germany)

We present a flow for 3D chip stack estimation based on 2D digital implementation tools. It comprises logic synthesis, netlist partitioning, TSV insertion, budgeting, place & route and cost analysis. TSVs are modeled as pairs of corresponding standard cells. The flow has been applied to a 16x SIMD vector-unit, which was partitioned in four tiers. A speed-up of 1:09 could be achieved against the 2D implementation. The total silicon area remained constant, while the footprint of the chip was reduced by a factor of four.