Petrides, Panayiotis; Trancoso, Pedro (Department of Computer Science, University of Cyprus, Nicosia, Cyprus)
Pratas, Frederico; Sousa, Leonel (INESC-ID/IST, Technical University of Lisbon, Lisbon, Portugal)
In recent years we have observed a shift in processor architectures towards chips with multiple cores, thus avoiding the power and complexity walls. The increasing number of cores is leading to major challenges such as processor configuration and management of such complex hardware. In order to achieve a better match between the hardware and the demands of different applications and their phases of execution, future processors will have to offer cores with different specifications which could even change dynamically at run-time. To address these issues we envision that for future processors the hardware will be packaged along with a virtualization layer that hides the hardware complexity and at the same time monitors the application behavior as to transparently improve its performance at run-time. The virtualization layer must be built in a modular way. Extra features, such as mechanisms to improve the execution of an application (e.g. data prefetching), and support for heterogeneous architectures (e.g. system with accelerators) are implemented into the virtualization layer as separate plug-in modules. As a case-study we present the benefits of implementing a bandwidth-aware scheduler as a mechanism of the virtualization layer.