Compact and Testable Circuits for Regular Functions
Konferenz: ARCS 2011 - 24th International Conference on Architecture of Computing Systems
22.02.2011 - 23.02.2011 in Como, Italy
Tagungsband: ARCS 2011
Seiten: 10Sprache: EnglischTyp: PDFPersönliche VDE-Mitglieder erhalten auf diesen Artikel 10% Rabatt
Bernasconi, Anna (Department of Computer Science, Università di Pisa, Italy)
Ciriani, Valentina (Department of Information Technologies, Università degli Studi di Milano, Italy)
We propose a new synthesis approach based on the SPP three-level logic minimization of D-reducible Boolean functions. This approach supplies a new tool for efficient minimization, based on the idea of exploiting a Boolean function regularity to get more compact expressions. D-reducible functions can be efficiently synthesized giving rise to new four-level logic forms called 'DRedSPP'. These forms are often smaller than the corresponding minimum SPP forms, and are fully testable under the Stuck-At Fault Model. Moreover, the computational time needed to derive a DRedSPP form for a D-reducible function f is nearly always less than the time required to derive an SPP representation of f.