An Optimized Timing and Control Flow Checker for Hard Real-Time Systems
Konferenz: ARCS 2013 - 26th International Conference on Architecture of Computing Systems 2013
19.02.2013 - 22.02.2013 in Prague, Czech Republic
Tagungsband: ARCS 2013
Seiten: 6Sprache: EnglischTyp: PDFPersönliche VDE-Mitglieder erhalten auf diesen Artikel 10% Rabatt
Wolf, Julian; Ungerer, Theo (University of Augsburg, Germany)
Dependability and safety are important requirements of embedded real-time systems. It is necessary to integrate mechanisms for an early fault detection to enable a potential error recovery before missing a deadline. Additionally, code size is an important concern regarding these systems. In this paper, we present optimization techniques for a timing and control flow checker designed for hard real-time systems. These improvements allow a massive reduction of the required overhead with only slight decreases of the fault detection capabilities. An experimental evaluation shows that the additional memory usage can be minimized by around 30%, while the execution time overhead is even reduced by around 50%. On the other hand, more than 57% of injected faults can still be detected by our technique – at an average detection latency of less than 30 processor cycles.