Gate Driver Architectures for High Speed Power Devices in Series Connection

Inhalt:
This paper presents a study on the gate driver circuitries that need to be implemented to drive power devices in series connection. More specifically, the propagation paths of parasitic currents through the gate driver circuitries, generated under very high switching speed, are studied in different configurations trying to minimize common mode currents. In a gate driver circuitry for a regular low side – high side switching cell configuration with one upper switch and one lower switch, the voltage transient dv/dt at the middle point applied across the primarysecondary parasitic capacitance of gate driver supplies and isolation units are the reason of the conducted EMI perturbations. In complex power converters, multi-cell, multi-level or even series connection of power devices, many driver circuits are required and implemented. Similarly, in such converters, there are several dv/dt sources generated at different floating points producing conducted EMI perturbations from the power part to the control part through many gate driver circuitries. Based on previous works, the paper analyses the best configuration to minimize parasitic currents, especially reducing the common mode currents in series connected transistors topologies. Simulations and practical results validate the analysis.