Analysis and Modeling of Efficiency Curve Dip in VRM with Low Output Inductance

Inhalt:
VRM performance requires a high efficiency solution in a small form factor. In order to achieve high performance, VRM designs are moving to low-inductance solutions, resulting in an efficiency dip at light load. For the first time, the efficiency curve dip is fully characterized, explained and simulated. This paper provides a simulation model of the efficiency dip in low output inductance VRM and validates the simulation model with experimental results. In addition, the impacts of switching frequency, output inductance, MOSFET technology and application conditions on the observed dip are discussed.