DC-link Impedance Model of Voltage Source Converter
Konferenz: PCIM Asia 2017 - International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management
27.06.2017 - 29.06.2017 in Shanghai, China
Tagungsband: PCIM Asia 2017
Seiten: 3Sprache: EnglischTyp: PDFPersönliche VDE-Mitglieder erhalten auf diesen Artikel 10% Rabatt
Danhong, Xue; Jinjun, Liu; Teng, Liu (School of Electrical Engineering, Xi'an Jiaotong University, China)
DC-link impedance model of voltage source converter (VSC) is needed in the stability analysis of high voltage dc (HVDC) system. This paper develops dc impedance model for the 3-phase PWM Voltage Source Converter when they are viewed from a dc terminal. The proposed modeling method uses traditional state-space averaging method to derive the small-signal impedance of the VSCs. The impedance models take converter controllers into account. The derived impedance models are validated by comparing frequency responses of the analytical model and the impedance measured at the dc terminal from a VSC model simulated in Saber.