A Target Platform Description Language for Parallel Code Generation
Konferenz: ARCS Workshop 2018 - 31th International Conference on Architecture of Computing Systems
09.04.2018 - 12.04.2018 in Braunschweig, Germany
Tagungsband: ARCS 2018
Seiten: 8Sprache: EnglischTyp: PDFPersönliche VDE-Mitglieder erhalten auf diesen Artikel 10% Rabatt
Schmitt, Christian; Hannig, Frank; Teich, Juergen (Hardware/Software Co-Design, Department of Computer Science, Friedrich Alexander University Erlangen-Nürnberg, Germany)
Today, facilities used for scientific computing are highly parallel and becoming more and more heterogeneous. This trend can be easily seen in the TOP500 list, where an increasing number of systems is equipped with accelerators, such as GPUs or many-cores. To achieve the best performance on such machines, special tweaking of the code is necessary, which takes time and expert knowledge of the hardware and corresponding optimization techniques. Domain-specific languages (DSLs) are a remedy to this dilemma by separating the algorithm specification from its implementation, leaving room for optimizations to be applied automatically by the DSL compiler. Thus, the compiler needs to have a profound knowledge of the target platform, e.g., available accelerators and how to program them, details of the network topology to optimize communication patterns, as well as CPU specifications for cache optimizations and vectorization. In this paper, we introduce our approach to modeling hardware and software information to provide platform details that our code generator requires to optimize and emit code for the solution of partial differential equations (PDEs) using the geometric multigrid method.