A Predictive Model to Investigate the Effects of Gate Driver on dV/dt in Series Connected SiC MOSFETs

Konferenz: PCIM Europe 2019 - International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management
07.05.2019 - 09.05.2019 in Nürnberg, Deutschland

Tagungsband: PCIM Europe 2019

Seiten: 8Sprache: EnglischTyp: PDF

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Lefranc, Pierre; Alves, Luciano F. S.; Jeannin, Pierre-Olivier; Sarrazin, Benoit; Nguyen, Van-Sang; Crebier, Jean-Christophe (Univ. Grenoble Alpes, CNRS, Grenoble INP – Institute of Engineering Univ. Grenoble Alpes, G2Elab, France)

Due to the increase of the switching speed of power devices, the impact of the gate driver parasitic capacitances has a influence on the dynamic behaviour in the switching cell. Here, the study is focused on the dynamic behaviour for series-connected SiC-MOSFET devices: a predictive model that considers the parasitic capacitances is developed and compared to simulation results. Then, experimental results validate the proposed modelling.