Optimization for the Number of Parallel-connected Switching Devices in High-efficiency High-power Converters

Inhalt:
This paper proposes an optimal design method for a high-efficiency and high-power converters. The system efficiency is improved by the design of the converters with the some small-current-rating parallel-connected devices, which achieve fast switching and low switching loss. The optimal number of parallel-connected SiC-MOSFETs for the maximum system efficiency is determined to achieve the reduction in both the conduction and the no-load loss due to drain-source parasitic capacitance of a SiC-MOSFET. The experimental results confirm that the optimal number of parallel-connected SiC-MOSFETs which leads to the smallest total device losses exists.