Degradation Pattern of Parallel Symmetrical and Asymmetrical Double-Trench SiC MOSFETs under Repetitive Short Circuits
Konferenz: PCIM Europe 2023 - International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management
09.05.2023-11.05.2023 in Nürnberg, Germany
doi:10.30420/566091111
Tagungsband: PCIM Europe 2023
Seiten: 6Sprache: EnglischTyp: PDF
Autoren:
Yu, Renze; Jahdi, Saeed; Yang, Juefei; Mellor, Phil (Department of Electrical Engineering, University of Bristol, Bristol, UK)
Ortiz Gonzalez, Jose; Alatise, Olayiwola (School of Engineering, University of Warwick, Coventry, UK)
Inhalt:
In practice, SiC MOSFET chips are often parallel-connected to promote the power rating. However, due to the potentially unequal circuit parameter and temperature distribution inside the power module, parallel devices suffer from different electrothermal stress, which may result in long-term reliability challenges. In this paper, the short circuit performance of parallel-connected Planar, Symmetrical and Asymmetrical Double-Trench SiC MOSFETs have been investigated. The impact of gate resistance and case temperature difference on current distribution of parallel SiC MOSFETs have been analyzed. The degradation pattern of key parameters of three types of devices have been studied.