Analysis of SiC MOSFET Degradation in Gate Switching Stress by Small-Signal Gate Impedance Method

Inhalt:
For the first time, this study combines measurements and simulations of the internal gate resistance (RGG) to elucidate the mechanisms behind threshold voltage (Vth) shift in SiC MOSFETs under Gate Switching Stress (GSS). Extensive gate impedance (ZGG) measurements were conducted across numerous samples using different measurement systems to ensure consistency in the experimental data. Coupled with ZGG measurements, finite-element simulations (TCAD) identified the nature and location of trap densities along the SiC-SiO2 interface. The dynamic evolution of these traps aligns with observed shifts in the empirical electrical parameters.