Optimizing Chip Area in Power Module Design: Comparison of Traditional and AI Surrogate Models for Thermal Resistance Calculation

Inhalt:
Optimizing chip area in power module design is crucial for balancing cost, performance and thermal management. This study introduces a methodology for chip area scaling based on junction temperature, calculated using power loss and thermal resistance values. Three different approaches for thermal resistance calculation are investigated: the hyperbolic scaling method, improved analytical method and AI-based surrogate model. The accuracy of each method is validated against FEM simulations. Results indicate that the AI-based surrogate model outperforms the other two methods, reaching ~99.93% accuracy with reduced computational time. The findings highlight the trade-offs between computational efficiency and accuracy, demonstrating that AI-driven models provide an effective alternative to FEM for rapid design iterations.