Optimisation of Silicon Carbide Gate Commutated Thyristors

Inhalt:
This paper presents the first demonstration and optimization of a Silicon Carbide (SiC) Gate Commutated Thyristor (GCT), which is suitable for ultra-high-voltage power applications. A novel device structure incorporating a High-Doped Base Stripe (HDBS) and a graded three-step buffer layer is proposed and thoroughly evaluated using TCAD simulations. Results indicate that the optimized structure significantly reduces critical reliability issues during turn-off, including cathode current overshoot (by 32%), dv/dt (by 55%), and turn-off losses (by 34%), with negligible trade-offs in conduction and blocking performance. Additionally, a unique hexagonal cathode mask layout is introduced to further improve current distribution uniformity and device stability. Initial fabrication results successfully validate the feasibility of key processes such as trench etching, lifetime enhancement, and ion implantation-based termination structures, highlighting both achievements and remaining fabrication challenges. This work provides essential design insights and technical foundations towards realizing high-performance SiC GCT devices.