MOS Transistor as a Distributed Resistive-Capacitive Element with Admittance of Fractional Order 0.5

Inhalt:
MOS transistor as a uniform distributed layer structure providing an input admittance of the fractional order of 0.5 is described. For the selected native n-channel MOS device in TSMC 65 nm technology, a circuit model including distributed channel resistance and distributed capacitance between gate, channel and bulk (body) is presented. The lumped parasitic resistances and capacitances of the electrodes are also considered in the model. The procedure for calculating the input admittance of the model based on the admittance matrix containing the transistor parameters is given. Magnitude and phase responses of the input admittance of the transistor depending on its dimensions and other, especially parasitic, properties are presented and analyzed. It is found that the half-order admittance appears in a certain frequency band and outside this band there is a deviation of the admittance phase from the required 45 degrees. The causes of these deviations and the possibility of their correction are discussed.