An Enhanced Parametric Testing Model for Optimizing Test Time and Cost in Semiconductor Chips

Inhalt:
Reducing test time and cost without compromising quality is a key challenge during high volume semiconductor production. This paper presents a novel adaptive test flow for semiconductor die-level parametric testing that significantly reduces test time and test cost without compromising quality. The proposed methodology was applied to 800 discrete Metal oxide semiconductor field effect transistor (MOSFET) (100 V / 316 A) dies, each undergoing eight critical parametric tests including threshold voltage, breakdown voltage, leakage current, and