>3 kV 4H-SiC MOSFETs with Design and Performance Evaluation
Konferenz: PCIM Asia New Delhi - The Agent of Change for the Indian Power Electronics Industry
09.12.2025-10.12.2025 in Dr. Ambedkar International Centre, New Delhi, India
doi:10.30420/566677042
Tagungsband: PCIM Asia New Delhi
Seiten: 10Sprache: EnglischTyp: PDF
Autoren:
Bhattacharya, Monikuntala; Jin, Michael; Yu, Hengyu; Housmand, Shiva; White, Marvin H.; Shimbori, Atsushi; Agarwal, Anant K.
Inhalt:
This study details the design and characterization of >3 kV planar 4H-SiC power MOSFETs featuring variable channel lengths and JFET widths in both inversion and accumulation modes. A hybrid JTE termination structure enabled robust blocking capability above 3 kV. Fabricated devices featured a uniform 50 nm gate oxide and stable operation across room and elevated temperatures. Compared to INVFETs, ACCUFETs demonstrated up to 18.75% reduction in specific on-resistance with reasonable threshold voltage, confirming their conduction advantages. However, switching characterization revealed stronger oscillations in ACCUFETs due to faster turn-on, indicating the importance of optimized gate-driver design. Body diode stress testing further highlighted reliability concerns on mid-to-high voltage power devices, mainly stemming from the high energy ion implantation. Overall, this work offers an in-depth evaluation of the performance and robustness of mid-voltage SiC power MOSFETs and delivers valuable design guidance for future power electronics systems.

