Low-Inductance DC-link Design dedicated to SiC-based Highly Integrated Inverters

Konferenz: CIPS 2020 - 11th International Conference on Integrated Power Electronics Systems
24.03.2020 - 26.03.2020 in Berlin, Deutschland

Tagungsband: ETG-Fb. 161: CIPS 2020

Seiten: 7Sprache: EnglischTyp: PDF

Schnack, Jasper; Golev, Victor; Goerdes, Jan Philipp; Schuemann, Ulf (University of Applied Sciences Kiel, Kiel, Germany)
Mallwitz, Regine (Technical University of Braunschweig, Brunswick, Germany)
Stahl, Stefan (Herwig Süncksen, FTCAP GmbH, Husum, Germany)

The equivalent series inductance of DC-link capacitors (ESL) presents a significant barrier to utilise the full potential of silicon carbide (SiC) power modules. This paper proposes design guidelines for the interconnection of DC-link film capacitors to the power module in order to achieve a small parasitic inductance in the current commutation loop. The results are considered to develop a low inductance DC-Link design. This paper contributes to the design of film capacitors as well as capacitor banks and the connection to the power module. Detailed analysis of different parts of the DC-link should provide a closer look to main parasitic design parameters of an inverter system. This paper concludes with the introduction of a low inductance integrated inverter system.