Exploration of DDR5 with the Open-Source Simulator DRAMSys
Konferenz: MBMV 2021 - 24. Workshop MBMV
18.03.2021 - 19.03.2021 in online
Tagungsband: ITG-Fb. 296: MBMV 2021
Seiten: 11Sprache: EnglischTyp: PDF
Steiner, Lukas; Wehn, Norbert (Technische Universität Kaiserslautern, Germany)
Jung, Matthias (Fraunhofer IESE, Kaiserslautern, Germany)
Over the last five decades, we have seen a continuous evolution in DRAM technology, always targeting lower cost per bit, higher device capacity, higher bandwidth, and lower power consumption. The most recent DRAM standard released by JEDEC in mid 2020 is DDR5. It exhibits several new features, for example two channels on a single DIMM, same-bank refresh, and data rates up to 8400 MT/s. As a result, DDR5 greatly enlarges the DRAM device options, while the selection of a suitable device heavily depends on the application. In this paper, we investigate the performance of the new DDR5 standard in depth, compare it to its predecessor DDR4, and derive key observations that help selecting a suitable DRAM configuration. We present a new DDR5 simulation model based on the open-source simulator DRAMSys. This is to the best of our knowledge the first DDR5 simulation model. The model is the base for all of our investigations.