3D-Integration process for back side illuminated image sensors

Inhalt:
The 3D integration of back-side illuminated sensors offers considerable advantages in terms of fill factor and enables large-area pixel arrays. This contribution provides an overview of the process steps of wafer bonding, wafer thinning, and electrical connection for the 3D integration of a back-side illuminated single-photon avalanche diode sensor for distance measurement. The 3D integration process involves oxide-to-oxide direct wafer bonding that creates a solid bond connec-tion at low, CMOS-compatible temperatures. Multi-stage chemical-mechanical polishing has been shown to planarize the surfaces of the sensor and readout wafers, enabling a void-free connection between them. Furthermore, a misalignment of <1 µm after wafer bonding can be achieved. The next step is to thin the bonded wafers by removing the inactive part of the sensor wafer. This is done by a combination of grinding and wet chemical etching. The challenge lies in precisely adjusting the layer thickness and minimizing variations across the wafer. As an alternative to the buried oxide of an SOI wafer, the p+/p- doping transition of epitaxial wafers is used as a etch stop. It is shown that an HNA etching solution, a mixture of hydrofluoric acid, nitric acid, and acetic acid, can be used to achieve a dopant concentration dependent etch stop in order to thin the sensor wafer to the required target thickness with minimal variations, even for large-area sensors. The electrical connection between the sensor and readout circuit wafers is realized by means of so-called micro-through-silicon vias (micrometerTSVs). It is shown that by electrochemically copper-filled micrometerTSVs a resistance of < 0.3 Ohms/via between the sensor and the readout circuit can be achieved.